Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 241
2.5 PIM Ports - Functional Description
2.5.1 General
Each pin except BKGD can act as general-purpose I/O. In addition most pins can act as an output or input
of a peripheral module.
2.5.2 Registers
A set of configuration registers is common to all ports with exception of the ADC port (Table 2-91). All
registers can be written at any time, however a specific configuration might not become active.
Example: Selecting a pullup device. This device does not become active while the port is used as a
push-pull output.
2.5.2.1 Data Register (PORTx, PTx)
This register holds the value driven out to the pin if the pin is used as a general-purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general-purpose output. When
reading this address, the buffered state of the pin is returned if the associated data direction register bit is
set to 0.
If the data direction register bits are set to 1, the contents of the data register is returned. This is independent
of any other configuration (Figure 2-64).
2.5.2.2 Input Register (PTIx)
This register is read-only and always returns the buffered state of the pin (Figure 2-64).
Table 2-91. Register availability per port
1
1
Each cell represents one register with individual configuration bits
Port
Data
(Portx,
PTx)
Input
(PTIx)
Data
Direction
(DDRx)
Pull
Enable
(PERx)
Polarity
Select
(PPSx)
Wired-
Or Mode
(WOMx)
Interrupt
Enable
(PIEx)
Interrupt
Flag
(PIFx)
A yes - yes
yes
----
Byes-yes ----
Cyes-yes ----
Dyes-yes ----
Eyes-yes ----
T yes yes yes yes yes - - -
S yes yes yes yes yes yes - -
M yes yes yes yes yes yes - -
P yes yes yes yes yes - yes yes
J yes yes yes yes yes - yes yes
AD yes yes yes yes yes - yes yes
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