NXP Semiconductors MC9S12G - Functional Description

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 389
10.4 Functional Description
10.4.1 Phase Locked Loop with Internal Filter (PLL)
The PLL is used to generate a high speed PLLCLK based on a low frequency REFCLK.
The REFCLK is by default the IRCCLK which is trimmed to f
IRC1M_TRIM
=1MHz.
If using the oscillator (OSCE=1) REFCLK will be based on OSCCLK. For increased flexibility, OSCCLK
can be divided in a range of 1 to 16 to generate the reference frequency REFCLK using the REFDIV[3:0]
bits. Based on the SYNDIV[5:0] bits the PLL generates the VCOCLK by multiplying the reference clock
by a 2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,
3, 4, 5, 6,... to 32 to generate the PLLCLK.
.
NOTE
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
Several examples of PLL divider settings are shown in Table 10-25. The following rules help to achieve
optimum stability and shortest lock time:
• Use lowest possible f
VCO
/ f
REF
ratio (SYNDIV value).
• Use highest possible REFCLK frequency f
REF
.
Table 10-25. Examples of PLL Divider Settings
f
osc
REFDIV[3:
0]
f
REF
REFFRQ[1:0] SYNDIV[5:0] f
VCO
VCOFRQ[1:0]
POSTDIV
[4:0]
f
PLL
f
bus
off $00 1MHz 00 $18 50MHz 01 $03 12.5MHz 6.25MHz
f
VCO
2f
REF
 SYNDIV 1+=
f
REF
f
OSC
REFDIV 1+
-------------------------------------
=
If oscillator is enabled (OSCE=1)
If oscillator is disabled (OSCE=0)
f
REF
f
IRC1M
=
f
PLL
f
VCO
POSTDIV 1+
-----------------------------------------
=
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
f
PLL
f
VCO
4
---------------
=
f
bus
f
PLL
2
-------------
=
If PLL is selected (PLLSEL=1)