NXP Semiconductors MC9S12G User Manual

48 KByte Flash Module (S12FTMRG48K1V1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 913
26.4.7 Interrupts
The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an ECC fault.
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
26.4.7.1 Description of Flash Interrupt Operation
The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with
the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed
description of the register bits involved, refer to Section 26.3.2.5, “Flash Configuration Register
(FCNFG)”, Section 26.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 26.3.2.7, “Flash
Status Register (FSTAT)”, and Section 26.3.2.8, “Flash Error Status Register (FERSTAT)”.
The logic used for generating the Flash module interrupts is shown in Figure 26-27.
Figure 26-27. Flash Module Interrupts Implementation
Table 26-66. Flash Interrupt Sources
Interrupt Source Interrupt Flag Local Enable
Global (CCR)
Mask
Flash Command Complete CCIF
(FSTAT register)
CCIE
(FCNFG register)
I Bit
ECC Double Bit Fault on Flash Read DFDIF
(FERSTAT register)
DFDIE
(FERCNFG register)
I Bit
ECC Single Bit Fault on Flash Read SFDIF
(FERSTAT register)
SFDIE
(FERCNFG register)
I Bit
Flash Error Interrupt Request
CCIF
CCIE
DFDIF
DFDIE
SFDIF
SFDIE
Flash Command Interrupt Request

NXP Semiconductors MC9S12G Specifications

General

Brand	NXP Semiconductors
Model	MC9S12G
Category	Microcontrollers
Language	English