NXP Semiconductors MC9S12G - Pm0; Ps4; Ps5; Ps6

Device Overview MC9S12G-Family
MC9S12G Family Reference Manual Rev.1.27
56 NXP Semiconductors
4PE0
1
EXTAL — — — — PUCR/PDPEE Down
5VSS— ———— — —
6PE1
1
XTAL — — — — PUCR/PDPEE Down
7 TEST — — — — N.A. RESET
pin Down
8 BKGD MODC — — — V
DDX
PUCR/BKPUE Up
9 PP0 KWP0 ETRIG0 API_EXTC
LK
PWM0 V
DDX
PERP/PPSP Disabled
10 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V
DDX
PERP/PPSP Disabled
11 PP2 KWP2 ETRIG2 PWM2 — V
DDX
PERP/PPSP Disabled
12 PP3 KWP3 ETRIG3 PWM3 — V
DDX
PERP/PPSP Disabled
13 PT3 IOC3 — — — V
DDX
PERT/PPST Disabled
14 PT2 IOC2 — — — V
DDX
PERT/PPST Disabled
15 PT1 IOC1 IRQ
——V
DDX
PERT/PPST Disabled
16 PT0 IOC0 XIRQ
——V
DDX
PERT/PPST Disabled
17 PAD0 KWAD0 AN0 — — V
DDA
PER1AD/PPS1AD Disabled
18 PAD1 KWAD1 AN1 — — V
DDA
PER1AD/PPS1AD Disabled
19 PAD2 KWAD2 AN2 — — V
DDA
PER1AD/PPS1AD Disabled
20 PAD3 KWAD3 AN3 — — V
DDA
PER1AD/PPS1AD Disabled
21 PAD4 KWAD4 AN4 — — V
DDA
PER1AD/PPS1AD Disabled
22 PAD5 KWAD5 AN5 ACMPO — V
DDA
PER1AD/PPS1AD Disabled
23 PAD6 KWAD6 AN6 ACMPP — V
DDA
PER1AD/PPS1AD Disabled
24 PAD7 KWAD7 AN7 ACMPM — V
DDA
PER1AD/PPS1AD Disabled
25 PS0 RXD0 — — — V
DDX
PERS/PPSS Up
26 PS1 TXD0 — — — V
DDX
PERS/PPSS Up
27 PS4 PWM4 MISO0 — — V
DDX
PERS/PPSS Up
28 PS5 IOC4 MOSI0 — — V
DDX
PERS/PPSS Up
29 PS6 IOC5 SCK0 — — V
DDX
PERS/PPSS Up
30 PS7 API_EXTCLK ECLK PWM5 SS0
V
DDX
PERS/PPSS Up
31 PM0 — — — — V
DDX
PERM/PPSM Disabled
Table 1-9. 32-Pin LQFP OPinout for S12GN16 and S12GN32
Function
<----lowest-----PRIORITY-----highest---->
Power
Supply
Internal Pull
Resistor
Package Pin Pin
2nd
Func.
3rd
Func.
4th
Func
5th
Func
CTRL
Reset
State