Device Overview MC9S12G-Family
MC9S12G Family Reference Manual Rev.1.27
144 NXP Semiconductors
1.12.3 Effects of Reset
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections
for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers.
1.12.3.1 Flash Configuration Reset Sequence Phase
On each reset, the Flash module holds CPU activity while loading Flash module registers from the Flash
memory. If double faults are detected in the reset phase, Flash module protection and security may be
active on leaving reset. This is explained in more detail in the Flash module Section 29.1, “Introduction”.
1.12.3.2 Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.12.3.3 I/O Pins
Refer to the PIM section for reset configurations of all peripheral module ports.
1.12.3.4 RAM
The RAM arrays are not initialized out of reset.
1.13 COP Configuration
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are
loaded from the Flash register FOPT. See Table 1-36 and Table 1-37 for coding. The FOPT register is
loaded from the Flash configuration field byte at global address 0x3_FF0E during the reset sequence.
Table 1-36. Initial COP Rate Configuration
NV[2:0] in
FOPT Register
CR[2:0] in
CPMUCOP Register
000 111
001 110
010 101
011 100
100 011
101 010
110 001
111 000
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