Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
150 NXP Semiconductors
2.1.2 Overview
The PIM establishes the interface between the peripheral modules and the I/O pins. It controls the electrical
pin properties as well as the signal prioritization and multiplexing on shared pins.
The family devices share same sets of package options (refer to device overview section) determining the
availability of pins and the related PIM memory maps. The corresponding devices are referenced
throughout this section by their group name as shown in Table 2-2.
2.1.3 Features
The PIM includes these distinctive registers:
• Data registers and data direction registers for ports A, B, C, D, E, T, S, M, P, J and AD when used
as general-purpose I/O
• Control registers to enable/disable pull devices and select pullups/pulldowns on ports T, S, M, P, J
and AD on per-pin basis
• Single control register to enable/disable pull devices on ports A, B, C, D and E, on per-port basis
and on BKGD pin
• Control registers to enable/disable open-drain (wired-or) mode on ports S and M
• Interrupt flag register for pin interrupts on ports P, J and AD
• Control register to configure IRQ pin operation
• Routing register to support programmable signal redirection in 20 TSSOP only
• Routing register to support programmable signal redirection in 100 LQFP package only
• Package code register preset by factory related to package in use, writable once after reset. Also
includes bit to reprogram routing of API_EXTCLK in all packages.
• Control register for free-running clock outputs
•
Table 2-2. Device Groups
Group Devices with same set of package options
G1
(100/64/48)
S12G240, S12GA240
S12G192, S12GA192
S12G128, S12GA128
S12G96, S12GA96
G2
(64/48/32)
S12G64, S12GA64
1
,
S12G48, S12GA48
1
,S12GN48
1
No 32 pin
G3
(48/32/20)
S12GN32, S12GNA32
1,2
S12GN16, S12GNA16
1,2
2
No 20 pin
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