NXP Semiconductors MC9S12G - Resets

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 395
10.5 Resets
10.5.1 General
All reset sources are listed in Table 10-26. Refer to MCU specification for related vector addresses and
priorities.
10.5.2 Description of Reset Operation
Upon detection of any reset of Table 10-26, an internal circuit drives the RESET pin low for 512 PLLCLK
cycles. After 512 PLLCLK cycles the RESET pin is released. The reset generator of the S12CPMU waits
for additional 256 PLLCLK cycles and then samples the RESET pin to determine the originating source.
Table 10-27 shows which vector will be fetched.
NOTE
While System Reset is asserted the PLLCLK runs with the frequency
f
VCORST
.
Table 10-26. Reset Summary
Reset Source Local Enable
Power-On Reset (POR) None
Low Voltage Reset (LVR) None
External pin RESET
None
Illegal Address Reset None
Clock Monitor Reset OSCE Bit in CPMUOSC register
COP Reset CR[2:0] in CPMUCOP register
Table 10-27. Reset Vector Selection
Sampled RESET Pin
(256 cycles after
release)
Oscillator monitor
fail pending
COP
time out
pending
Vector Fetch
100 POR
LVR
Illegal Address Reset
External pin RESET
1 1 X Clock Monitor Reset
1 0 1 COP Reset
0XX POR
LVR
Illegal Address Reset
External pin RESET