Digital Analog Converter (DAC_8B5V)
MC9S12G Family Reference Manual Rev.1.27
566 NXP Semiconductors
17.5.4 Mode “Unbuffered DAC”
The “Unbuffered DAC” mode is selected by DACCNTL.DACM[2:0] = 0x4. During this mode the
unbuffered analog voltage from the DAC resistor network output is available on the DACU output pin.
The operational amplifier is disabled and the operational amplifier signals are disconnected from the AMP
pins. For decoding of the control signals see Table 17-7.
17.5.5 Mode “Unbuffered DAC with Operational Amplifier”
The “Unbuffered DAC with Operational Amplifier” mode is selected by DACCTL.DACM[2:0] = 0x5.
During this mode the DAC resistor network and the operational amplifier are enabled and usable
independent from each other. The unbuffered analog voltage from the DAC resistor network output is
available on the DACU output pin.
The operational amplifier is disconnected from the DAC resistor network. All required amplifier signals,
AMP, AMPP and AMPM are available on the pins. The connection between the amplifier output and the
negative amplifier input is open. For decoding of the control signals see Table 17-7.
17.5.6 Mode “Buffered DAC”
The “Buffered DAC” mode is selected by DACCTL.DACM[2:0] = 0x7. During this is mode the DAC
resistor network and the operational amplifier are enabled. The analog output voltage from the DAC
resistor network output is buffered by the operational amplifier and is available on the AMP output pin.
The DAC resistor network output is disconnected from the DACU pin. For the decoding of the control
signals see Table 17-7.
17.5.7 Analog output voltage calculation
The DAC can provide an analog output voltage in two different voltage ranges:
• FVR = 0, reduced voltage range
The DAC generates an analog output voltage inside the range from 0.1 x (VRH - VRL) + VRL to
0.9 x (VRH-VRL) + VRL with a resolution ((VRH-VRL) x 0.8) / 256, see equation below:
analog output voltage = VOLATGE[7:0] x ((VRH-VRL) x 0.8) / 256) + 0.1 x (VRH-VRL) + VRL Eqn. 17-1
• FVR = 1, full voltage range
The DAC generates an analog output voltage inside the range from VRL to VRH with a resolution
(VRH-VRL) / 256, see equation below:
analog output voltage = VOLTAGE[7:0] x (VRH-VRL) / 256 +VRL Eqn. 17-2
To Next Page
Loading...
Need help?
General
