MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 259
Chapter 5
S12G Memory Map Controller (S12GMMCV1)
Table 5-1. Revision History Table
5.1 Introduction
The S12GMMC module controls the access to all internal memories and peripherals for the CPU12 and
S12SBDM module. It regulates access priorities and determines the address mapping of the on-chip
resources. Figure 5-1 shows a block diagram of the S12GMMC module.
5.1.1 Glossary
5.1.2 Overview
The S12GMMC connects the CPU12’s and the S12SBDM’s bus interfaces to the MCU’s on-chip resources
(memories and peripherals). It arbitrates the bus accesses and determines all of the MCU’s memory maps.
Furthermore, the S12GMMC is responsible for constraining memory accesses on secured devices and for
selecting the MCU’s functional mode.
Rev. No.
(Item No.)
Date
(Submitted By)
Sections
Affected
Substantial Change(s)
01.02 20-May 2010 Updates for S12VR48 and S12VR64
Table 5-2. Glossary Of Terms
Term Definition
Local Addresses Address within the CPU12’s Local Address Map (Figure 5-11)
Global Address Address within the Global Address Map (Figure 5-11)
Aligned Bus Access Bus access to an even address.
Misaligned Bus Access Bus access to an odd address.
NS Normal Single-Chip Mode
SS Special Single-Chip Mode
Unimplemented Address Ranges Address ranges which are not mapped to any on-chip resource.
NVM Non-volatile Memory; Flash or EEPROM
IFR NVM Information Row. Refer to FTMRG Block Guide
To Next Page
Loading...
Need help?
General
