Device Overview MC9S12G-Family
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 35
1.3.8 System Integrity Support
• Power-on reset (POR)
• System reset generation
• Illegal address detection with reset
• Low-voltage detection with interrupt or reset
• Real time interrupt (RTI)
• Computer operating properly (COP) watchdog
— Configurable as window COP for enhanced failure detection
— Initialized out of reset using option bits located in flash memory
• Clock monitor supervising the correct function of the oscillator
1.3.9 Timer (TIM)
• Up to eight x 16-bit channels for input capture or output compare
• 16-bit free-running counter with 7-bit precision prescaler
• In case of eight channel timer Version an additional 16-bit pulse accumulator is available
1.3.10 Pulse Width Modulation Module (PWM)
• Up to eight channel x 8-bit or up to four channel x 16-bit pulse width modulator
— Programmable period and duty cycle per channel
— Center-aligned or left-aligned outputs
— Programmable clock select logic with a wide range of frequencies
1.3.11 Controller Area Network Module (MSCAN)
• 1 Mbit per second, CAN 2.0 A, B software compatible
— Standard and extended data frames
— 0–8 bytes data length
— Programmable bit rate up to 1 Mbps
• Five receive buffers with FIFO storage scheme
• Three transmit buffers with internal prioritization
• Flexible identifier acceptance filter programmable as:
— 2 x 32-bit
— 4 x 16-bit
— 8 x 8-bit
• Wakeup with integrated low pass filter option
• Loop back for self test
• Listen-only mode to monitor CAN bus
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