NXP Semiconductors MC9S12G - External Signal Description

S12S Debug Module (S12SDBGV2)
MC9S12G Family Reference Manual Rev.1.27
308 NXP Semiconductors
8.2 External Signal Description
There are no external signals associated with this module.
8.3 Memory Map and Registers
8.3.1 Module Memory Map
A summary of the registers associated with the DBG sub-block is shown in Figure 8-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
Address Name Bit 7 6 5 4 3 2 1 Bit 0
0x0020 DBGC1
R
ARM
00
BDM DBGBRK
0
COMRV
WTRIG
0x0021 DBGSR
R
1
TBF 0 0 0 0 SSF2 SSF1 SSF0
W
0x0022 DBGTCR
R0
TSOURCE
00
TRCMOD
0
TALIGN
W
0x0023 DBGC2
R000000
ABCM
W
0x0024 DBGTBH
R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
0x0025 DBGTBL
RBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
W
0x0026 DBGCNT
R
1
TBF 0 CNT
W
0x0027 DBGSCRX
R0 0 0 0
SC3 SC2 SC1 SC0
W
0x0027 DBGMFR
R00000MC2MC1MC0
W
2
0x0028
DBGACTL
R
SZE SZ TAG BRK RW RWE NDB COMPE
W
3
0x0028
DBGBCTL
R
SZE SZ TAG BRK RW RWE
0
COMPE
W
4
0x0028
DBGCCTL
R0 0
TAG BRK RW RWE
0
COMPE
W
0x0029 DBGXAH
R000000
Bit 17 Bit 16
W
0x002A DBGXAM
R
Bit 15 14 13 12 11 10 9 Bit 8
W
0x002B DBGXAL
R
Bit 7654321Bit 0
W
Figure 8-2. Quick Reference to DBG Registers