48 KByte Flash Module (S12FTMRG48K1V1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 869
26.3 Memory Map and Registers
This section describes the memory map and registers for the Flash module. Read data from unimplemented
memory space in the Flash module is undefined. Write access to unimplemented or reserved memory space
in the Flash module will be ignored by the Flash module.
CAUTION
Writing to the Flash registers while a Flash command is executing (that is
indicated when the value of flag CCIF reads as ’0’) is not allowed. If such
action is attempted the write operation will not change the register value.
Writing to the Flash registers is allowed when the Flash is not busy
executing commands (CCIF = 1) and during initialization right after reset,
despite the value of flag CCIF in that case (refer to Section 26.6 for a
complete description of the reset sequence).
.
26.3.1 Module Memory Map
The S12 architecture places the P-Flash memory between global addresses 0x3_4000 and 0x3_FFFF as
shown in Table 26-3 .The P-Flash memory map is shown in Figure 26-2.
Table 26-2. FTMRG Memory Map
Global Address (in Bytes) Size
(Bytes)
Description
0x0_0000 - 0x0_03FF
1,024
Register Space
0x0_0400 – 0x0_09FF 1,536 EEPROM Memory
0x0_0A00 – 0x0_0BFF 512 FTMRG reserved area
0x0_4000 – 0x0_7FFF 16,284 NVMRES
1
=1 : NVM Resource area (see Figure 26-3)
1
See NVMRES description in Section 26.4.3
0x3_0000 – 0x3_3FFF 16,384 FTMRG reserved area
0x3_4000 – 0x3_FFFF 49,152 P-Flash Memory
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