NXP Semiconductors MC9S12G - Pin BKGD

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 163
2.3.1 Pin BKGD
2.3.2 Pins PA7-0
2.3.3 Pins PB7-0
2.3.4 Pins PC7-0
NOTE
• When using AMPM1, AMPP1 or DACU1 please refer to section 2.6.1,
“Initialization”.
Table 2-5. Pin BKGD
BKGD • The BKGD pin is associated with the BDM module in all packages. During reset, the BKGD pin is used
as MODC input.
Table 2-6. Port A Pins PA7-0
PA7-PA0 • These pins feature general-purpose I/O functionality only.
Table 2-7. Port B Pins PB7-0
PB7-PB6 • These pins feature general-purpose I/O functionality only.
PB5 • 100 LQFP: The XIRQ signal is mapped to this pin when used with the XIRQ interrupt function. The
interrupt is enabled by clearing the X mask bit in the CPU Condition Code register. The I/O state of the
pin is forced to input level upon the first clearing of the X bit and held in this state even if the bit is set
again. A STOP or WAIT recovery with the X bit set (refer to CPU12/CPU12X Reference Manual) is not
available.
• Signal priority:
100 LQFP: XIRQ
> GPO
PB4 • 100 LQFP: The IRQ signal is mapped to this pin when used with the IRQ interrupt function. If enabled
(IRQEN=1) the I/O state of the pin is forced to be an input.
• Signal priority:
100 LQFP: IRQ
> GPO
PB3 • This pin features general-purpose I/O functionality only.
PB2 • 100 LQFP: The ECLKX2 signal is mapped to this pin when used with the external clock function. The
enabled ECLKX2 signal forces the I/O state to an output.
• Signal priority:
100 LQFP: ECLKX2 > GPO
PB1 • 100 LQFP: The API_EXTCLK signal is mapped to this pin when used with the external clock function.
If the Autonomous Periodic Interrupt clock is enabled and routed here the I/O state is forced to output.
• Signal priority:
100 LQFP: API_EXTCLK > GPO
PB0 • 100 LQFP: The ECLK signal is mapped to this pin when used with the external clock function. The
enabled ECLK signal forces the I/O state to an output.
• Signal priority:
100 LQFP: ECLK > GPO