NXP Semiconductors MC9S12G - Register Descriptions

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 363
10.3.2 Register Descriptions
This section describes all the S12CPMU registers and their individual bits.
Address order is as listed in Figure 10-3.
10.3.2.1 S12CPMU Synthesizer Register (CPMUSYNR)
The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency
range.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write
has no effect.
NOTE
Writing to this register clears the LOCK and UPOSC status bits.
NOTE
f
VCO
must be within the specified VCO frequency lock range. Bus
frequency f
bus
must not exceed the specified maximum.
The VCOFRQ[1:0] bits are used to configure the VCO gain for optimal stability and lock time. For correct
PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in Table 10-1. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional
PLL (no locking and/or insufficient stability).
0x0034
76543210
R
VCOFRQ[1:0] SYNDIV[5:0]
W
Reset01011000
Figure 10-4. S12CPMU Synthesizer Register (CPMUSYNR)
Table 10-1. VCO Clock Frequency Selection
VCOCLK Frequency Ranges VCOFRQ[1:0]
32MHz <= f
VCO
<= 48MHz 00
48MHz < f
VCO
<= 50MHz 01
Reserved 10
f
VCO
2f
REF
 SYNDIV 1+=
If PLL has locked (LOCK=1)