NXP Semiconductors MC9S12G - Page 360

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
362 NXP Semiconductors
0x003B CPMURTI
R
RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
0x003C CPMUCOP
R
WCOP RSBCK
000
CR2 CR1 CR0
W WRTMASK
0x003D
RESERVEDCP
MUTEST0
R0 0 0 0 0 0 0 0
W
0x003E
RESERVEDCP
MUTEST1
R0 0 0 0 0 0 0 0
W
0x003F
CPMU
ARMCOP
R0 0 0 0 0 0 0 0
W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x02F0 RESERVED
R0 0 0 0 0 0 0 0
W
0x02F1
CPMU
LVCTL
R0 0 0 0 0 LVDS
LVIE LVIF
W
0x02F2
CPMU
APICTL
R
APICLK
00
APIES APIEA APIFE APIE APIF
W
0x02F3 CPMUACLKTR
R
ACLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0
00
W
0x02F4 CPMUAPIRH
R
APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8
W
0x02F5 CPMUAPIRL
R
APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0
W
0x02F6
RESERVEDCP
MUTEST3
R 0 0 0 0 0 0 0 0
W
0x02F7 RESERVED
R0 0 0 0 0 0 0 0
W
0x02F8
CPMU
IRCTRIMH
R
TCTRIM[4:0]
0
IRCTRIM[9:8]
W
0x02F9
CPMU
IRCTRIML
R
IRCTRIM[7:0]
W
0x02FA CPMUOSC
R
OSCE Reserved
OSCPINS_
EN
Reserved
W
0x02FB CPMUPROT
R0 0 0 0 0 0 0
PROT
W
0x02FC
RESERVEDCP
MUTEST2
R0 0 0 0 0 0 0 0
W
Addres
s
Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Figure 10-3. CPMU Register Summary