Serial Peripheral Interface (S12SPIV5)
MC9S12G Family Reference Manual Rev.1.27
694 NXP Semiconductors
21.2.2 MISO — Master In/Slave Out Pin
This pin is used to transmit data out of the SPI module when it is configured as a slave and receive data
when it is configured as master.
21.2.3 SS — Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is configured as a master and it is used as an input to receive the slave select
signal when the SPI is configured as slave.
21.2.4 SCK — Serial Clock Pin
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
21.3 Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the SPI.
21.3.1 Module Memory Map
The memory map for the SPI is given in Figure 21-2. The address listed for each register is the sum of a
base address and an address offset. The base address is defined at the SoC level and the address offset is
defined at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
Register
Name
Bit 76 5 4 3 2 1Bit 0
0x0000
SPICR1
R
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
W
0x0001
SPICR2
R0
XFRW
0
MODFEN BIDIROE
0
SPISWAI SPC0
W
0x0002
SPIBR
R0
SPPR2 SPPR1 SPPR0
0
SPR2 SPR1 SPR0
W
0x0003
SPISR
R SPIF 0 SPTEF MODF 0 0 0 0
W
0x0004
SPIDRH
R R15 R14 R13 R12 R11 R10 R9 R8
T15 T14 T13 T12 T11 T10 T9 T8W
= Unimplemented or Reserved
Figure 21-2. SPI Register Summary
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