S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
360 NXP Semiconductors
NOTE
NXP recommends an evaluation of the application board and chosen
resonator or crystal by the resonator or crystal supplier.
The loop controlled circuit (XOSCLCP) is not suited for overtone
resonators and crystals.
10.2.3 VDDR — Regulator Power Input Pin
Pin V
DDR
is the power input of IVREG. All currents sourced into the regulator loads flow through this pin.
An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between V
DDR
and V
SS
can smooth
ripple on V
DDR
.
10.2.4 VSS — Ground Pin
V
SS
must be grounded.
10.2.5 VDDA, VSSA — Regulator Reference Supply Pins
Pins V
DDA
and V
SSA
are used to supply the analog parts of the regulator.
Internal precision reference circuits are supplied from these signals.
An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between V
DDA
and V
SSA
can improve
the quality of this supply.
10.2.6 VDDX, VSSX— Pad Supply Pins
This supply domain is monitored by the Low Voltage Reset circuit.
An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDX and VSSX can improve
the quality of this supply.
NOTE
Depending on the device package following device supply pins are maybe
combined into one pin: VDDR, VDDX and VDDA.
Depending on the device package following device supply pins are maybe
combined into one pin: VSS, VSSX and VSSA.
Please refer to the device Reference Manual for information if device supply
pins are combined into one supply pin for certain packages and which
supply pins are combined together.
An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between
the combined supply pin pair can improve the quality of this supply.
To Next Page
Loading...
Need help?
General
