Timer Module (TIM16B6CV3)
MC9S12G Family Reference Manual Rev.1.27
736 NXP Semiconductors
Setting OCPDx to zero allows the internal register to drive the programmed state to OCx. This allows a
glitch free switch over of port from general purpose I/O to timer output once the OCPDx bit is set to zero.
22.5 Resets
The reset state of each individual bit is listed within Section 22.3, “Memory Map and Register Definition”
which details the registers and their bit fields
22.6 Interrupts
This section describes interrupts originated by the TIM16B6CV3 block. Table 22-18 lists the interrupts
generated by the TIM16B6CV3 to communicate with the MCU.
The TIM16B6CV3 could use up to 7 interrupt vectors. The interrupt vector offsets and interrupt numbers
are chip dependent.
22.6.1 Channel [5:0] Interrupt (C[5:0]F)
This active high outputs will be asserted by the module to request a timer channel 7 – 0 interrupt. The TIM
block only generates the interrupt and does not service it. Only bits related to implemented channels are
valid.
22.6.2 Timer Overflow Interrupt (TOF)
This active high output will be asserted by the module to request a timer overflow interrupt. The TIM block
only generates the interrupt and does not service it.
Table 22-18. TIM16B6CV3 Interrupts
Interrupt Offset Vector Priority Source Description
C[5:0]F — — — Timer Channel 5–0 Active high timer channel interrupts 5–0
TOF — — — Timer Overflow Timer Overflow interrupt
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