NXP Semiconductors MC9S12G - Prescaler

Timer Module (TIM16B6CV3)
MC9S12G Family Reference Manual Rev.1.27
734 NXP Semiconductors
Figure 22-22. Detailed Timer Block Diagram
22.4.1 Prescaler
The prescaler divides the Bus clock by 1, 2, 4, 8, 16, 32, 64 or 128. The prescaler select bits, PR[2:0], select
the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
The prescaler divides the Bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system
control register 2 (TSCR2) are set to define a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32,
64 and 128 when the PRNT bit in TSCR1 is disabled.
PRESCALER
CHANNEL 0
IOC0 PIN
16-BIT COUNTER
LOGIC
PR[2:1:0]
TC0
16-BIT COMPARATOR
TCNT(hi):TCNT(lo)
CHANNEL 1
TC1
16-BIT COMPARATOR
INTERRUPT
LOGIC
TOF
TOI
C0F
C1F
EDGE
DETECT
IOC1 PIN
LOGIC
EDGE
DETECT
CxF
CHANNELn-1
TCn-1
16-BIT COMPARATOR Cn-1F
IOCn-1 PIN
LOGIC
EDGE
DETECT
OM:OL0
TOV0
OM:OL1
TOV1
OM:OL7
TOV7
EDG1A EDG1B
EDG7A
EDG7B
EDG0B
CxI
CH. n-1COMPARE
CH.n-1 CAPTURE
CH. 1 CAPTURE
MUX
CLK[1:0]
PACLK
PACLK/256
PACLK/65536
IOC1 PIN
IOC0 PIN
IOCn-1 PIN
TE
CH. 1 COMPARE
CH. 0COMPARE
CH. 0 CAPTURE
PA INPUT
CHANNEL2
EDG0A
IOC0
IOC1
IOCn-1
TOF
C0F
C1F
Cn-1F
MUX
PRE-PRESCALER
PTPSR[7:0]
tim source Clock
1
0
PRNT
n is channels number.