NXP Semiconductors MC9S12G - Chapter 14 Analog-To-Digital Converter (ADC12 B12 CV2)

MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 481
Chapter 14
Analog-to-Digital Converter (ADC12B12CV2)
Revision History
Version
Number
Revision
Date
Effective
Date
Author Description of Changes
V02.00 13 May 2009 13 May 2009
Initial version copied from V01.06,
changed unused Bits in ATDDIEN to read logic 1
V02.01 30.Nov 2009 30.Nov 2009
Updated Table 14-15 Analog Input Channel Select Coding -
description of internal channels.
Updated register ATDDR (left/right justified result) description
in section 14.3.2.12.1/14-502 and 14.3.2.12.2/14-503 and
added table Table 14-21 to improve feature description.
V02.02 09 Feb 2010 09 Feb 2010
Fixed typo in Table 14-9- conversion result for 3mV and 10bit
resolution
V02.03 26 Feb 2010 26 Feb 2010
Corrected Table 14-15 Analog Input Channel Select Coding -
description of internal channels.
V02.04 14 Apr 2010 14 Apr 2010
Corrected typos to be in-line with SoC level pin naming
conventions for VDDA, VSSA, VRL and VRH.
V02.05 25 Aug 2010 25 Aug 2010
Removed feature of conversion during STOP and general
wording clean up done in Section 14.4, “Functional
Description
V02.06 09 Sep 2010 09 Sep 2010 Update of internal only information.
V02.07 11 Feb 2011 11 Feb 2011
Connectivity Information regarding internal channel_6 added
to Table 14-15.
V02.08 29 Mar 2011 29 Mar 2011
Fixed typo in bit description field Table 14-14 for bits CD, CC,
CB, CA. Last sentence contained a wrong highest channel
number (it is not AN7 to AN0 instead it is AN11 to AN0).
V02.09 22. Jun 2012 22. Jun 2012
Update of register write access information in section
14.3.2.9/14-500.
V02.10 29 Jun 2012 29. Jun 2012 Removed IP name in block diagram Figure 14-1
V02.11 02 Oct 2012 02 Oct 2012
Added user information to avoid maybe false external trigger
events when enabling the external trigger mode
(Section 14.4.2.1, “External Trigger Input).