NXP Semiconductors MC9S12G User Manual

Device Overview MC9S12G-Family
MC9S12G Family Reference Manual Rev.1.27
32 NXP Semiconductors
1.2.2 Chip-Level Features
On-chip modules available within the family include the following features:
• S12 CPU core
• Up to 240 Kbyte on-chip flash with ECC
• Up to 4 Kbyte EEPROM with ECC
• Up to 11 Kbyte on-chip SRAM
• Phase locked loop (IPLL) frequency multiplier with internal filter
• 4–16 MHz amplitude controlled Pierce oscillator
• 1 MHz internal RC oscillator
• Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture,
output compare, counter, and pulse accumulator functions
• Pulse width modulation (PWM) module with up to eight x 8-bit channels
• Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter
(ADC)
• Up to two 8-bit digital-to-analog converters (DAC)
• Up to one 5V analog comparator (ACMP)
• Up to three serial peripheral interface (SPI) modules
• Up to three serial communication interface (SCI) modules supporting LIN communications
• Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol
2.0A/B)
• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages
• Autonomous periodic interrupt (API)
• Precision fixed voltage reference for ADC conversions
• Optional reference voltage attenuator module to increase ADC accuracy
1.3 Module Features
The following sections provide more details of the modules implemented on the MC9S12G-Family family.
DAC0 — — — Yes Yes Yes Yes
DAC1 — — — Yes Yes Yes Yes
AC MP Yes Yes Yes Yes Yes — —
Total GPIO 14 26 40 40 54 86 86
Table 1-2. Maximum Peripheral Availability per Package
Peripheral 20 TSSOP 32 LQFP 48 QFN 48 LQFP 64 LQFP 100 LQFP KGD (Die)

NXP Semiconductors MC9S12G Specifications

General

Brand	NXP Semiconductors
Model	MC9S12G
Category	Microcontrollers
Language	English