Device Overview MC9S12G-Family
MC9S12G Family Reference Manual Rev.1.27
50 NXP Semiconductors
1.7.2.23 Internal Clock outputs
1.7.2.23.1 ECLK
This signal is associated with the output of the divided bus clock (ECLK).
NOTE
This feature is only intended for debug purposes at room temperature.
It must not be used for clocking external devices in an application.
1.7.2.23.2 ECLKX2
This signal is associated with the output of twice the bus clock (ECLKX2).
NOTE
This feature is only intended for debug purposes at room temperature.
It must not be used for clocking external devices in an application.
1.7.2.23.3 API_EXTCLK
This signal is associated with the output of the API clock (API_EXTCLK).
1.7.2.24 IOC[7:0] Signals
The signals IOC[7:0] are associated with the input capture or output compare functionality of the timer
(TIM) module.
1.7.2.25 IRQ
This signal is associated with the maskable IRQ interrupt.
1.7.2.26 XIRQ
This signal is associated with the non-maskable XIRQ interrupt.
1.7.2.27 ETRIG[3:0]
These signals are inputs to the Analog-to-Digital Converter. Their purpose is to trigger ADC conversions.
1.7.3 Power Supply Pins
MC9S12G power and ground pins are described below. Because fast signal transitions place high,
short-duration current demands on the power supply, use bypass capacitors with high-frequency
characteristics and place them as close to the MCU as possible.
NOTE
All ground pins must be connected together in the application.
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