NXP Semiconductors MC9S12G User Manual

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 361
10.2.7 VDD — Internal Regulator Output Supply (Core Logic)
Node VDD is a device internal supply output of the voltage regulator that provides the power supply for
the core logic.
This supply domain is monitored by the Low Voltage Reset circuit.
10.2.8 VDDF — Internal Regulator Output Supply (NVM Logic)
Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for
the NVM logic.
This supply domain is monitored by the Low Voltage Reset circuit
10.2.9
API_EXTCLK
— API external clock output pin
This pin provides the signal selected via APIES and is enabled with APIEA bit. See device specification
to which pin it connects.
10.3 Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12CPMU.
10.3.1 Module Memory Map
The S12CPMU registers are shown in Figure 10-3.
Addres
s
Name Bit 7 6 5 4 3 2 1 Bit 0
0x0034
CPMU
SYNR
R
VCOFRQ[1:0] SYNDIV[5:0]
W
0x0035
CPMU
REFDIV
R
REFFRQ[1:0]
00
REFDIV[3:0]
W
0x0036
CPMU
POSTDIV
R0 0 0
POSTDIV[4:0]
W
0x0037 CPMUFLG
R
RTIF PORF LVRF LOCKIF
LOCK
ILAF OSCIF
UPOSC
W
0x0038 CPMUINT
R
RTIE
00
LOCKIE
00
OSCIE
0
W
0x0039 CPMUCLKS
R
PLLSEL PSTP
0
COP
OSCSEL1
PRE PCE
RTI
OSCSEL
COP
OSCSEL0
W
0x003A CPMUPLL
R0 0
FM1 FM0
00 0 0
W
= Unimplemented or Reserved
Figure 10-3. CPMU Register Summary

NXP Semiconductors MC9S12G Specifications

General

Brand	NXP Semiconductors
Model	MC9S12G
Category	Microcontrollers
Language	English