Security (S12XS9SECV2)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 349
NOTE
Please refer to the Flash block guide for actual security configuration (in
section “Flash Module Security”).
9.1.4 Operation of the Secured Microcontroller
By securing the device, unauthorized access to the EEPROM and Flash memory contents can be
prevented. However, it must be understood that the security of the EEPROM and Flash memory contents
also depends on the design of the application program. For example, if the application has the capability
of downloading code through a serial port and then executing that code (e.g. an application containing
bootloader code), then this capability could potentially be used to read the EEPROM and Flash memory
contents even when the microcontroller is in the secure state. In this example, the security of the
application could be enhanced by requiring a challenge/response authentication before any code can be
downloaded.
Secured operation has the following effects on the microcontroller:
9.1.4.1 Normal Single Chip Mode (NS)
• Background debug module (BDM) operation is completely disabled.
• Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for
details.
• Tracing code execution using the DBG module is disabled.
9.1.4.2 Special Single Chip Mode (SS)
• BDM firmware commands are disabled.
• BDM hardware commands are restricted to the register space.
• Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for
details.
• Tracing code execution using the DBG module is disabled.
Special single chip mode means BDM is active after reset. The availability of BDM firmware commands
depends on the security state of the device. The BDM secure firmware first performs a blank check of both
the Flash memory and the EEPROM. If the blank check succeeds, security will be temporarily turned off
and the state of the security bits in the appropriate Flash memory location can be changed If the blank
check fails, security will remain active, only the BDM hardware commands will be enabled, and the
accessible memory space is restricted to the peripheral register area. This will allow the BDM to be used
Table 9-4. Security Bits
SEC[1:0] Security State
00 1 (secured)
01 1 (secured)
10 0 (unsecured)
11 1 (secured)
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