NXP Semiconductors MC9S12G - Page 362

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
364 NXP Semiconductors
10.3.2.2 S12CPMU Reference Divider Register (CPMUREFDIV)
The CPMUREFDIV register provides a finer granularity for the PLL multiplier steps when using the
external oscillator as reference.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write
has no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
The REFFRQ[1:0] bits are used to configure the internal PLL filter for optimal stability and lock time. For
correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in Table 10-2.
If IRC1M is selected as REFCLK (OSCE=0) the PLL filter is fixed configured for the 1MHz <= f
REF
<=
2MHz range. The bits can still be written but will have no effect on the PLL filter configuration.
For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking
and/or insufficient stability).
Reserved 11
0x0035
76543210
R
REFFRQ[1:0]
00
REFDIV[3:0]
W
Reset00001111
Figure 10-5. S12CPMU Reference Divider Register (CPMUREFDIV)
Table 10-1. VCO Clock Frequency Selection
VCOCLK Frequency Ranges VCOFRQ[1:0]
f
REF
f
OSC
REFDIV 1+
-------------------------------------
=
If XOSCLCP is enabled (OSCE=1)
If XOSCLCP is disabled (OSCE=0)
f
REF
f
IRC1M
=