NXP Semiconductors MC9S12G - Page 363

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 365
10.3.2.3 S12CPMU Post Divider Register (CPMUPOSTDIV)
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
Read: Anytime
Write: Anytime if PLLSEL=1. Else write has no effect.
10.3.2.4 S12CPMU Flags Register (CPMUFLG)
This register provides S12CPMU status bits and flags.
Table 10-2. Reference Clock Frequency Selection if OSC_LCP is enabled
REFCLK Frequency Ranges
(OSCE=1)
REFFRQ[1:0]
1MHz <= f
REF
<= 2MHz 00
2MHz < f
REF
<= 6MHz 01
6MHz < f
REF
<= 12MHz 10
f
REF
>12MHz 11
0x0036
76543210
R0 0 0
POSTDIV[4:0]
W
Reset00000011
= Unimplemented or Reserved
Figure 10-6. S12CPMU Post Divider Register (CPMUPOSTDIV)
f
PLL
f
VCO
POSTDIV 1+
-----------------------------------------
=
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
f
PLL
f
VCO
4
---------------
=
f
bus
f
PLL
2
-------------
=
If PLL is selected (PLLSEL=1)