NXP Semiconductors MC9S12G - Page 394

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
396 NXP Semiconductors
The internal reset of the MCU remains asserted while the reset generator completes the 768 PLLCLK
cycles long reset sequence. In case the RESET pin is externally driven low for more than these 768
PLLCLK cycles (External Reset), the internal reset remains asserted longer.
Figure 10-34. RESET Timing
10.5.2.1 Clock Monitor Reset
If the external oscillator is enabled (OSCE=1) in case of loss of oscillation or the oscillator frequency is
below the failure assert frequency f
CMFA
(see device electrical characteristics for values), the S12CPMU
generates a Clock Monitor Reset.In Full Stop Mode the external oscillator and the clock monitor are
disabled.
10.5.2.2 Computer Operating Properly Watchdog (COP) Reset
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. When the COP is being used, software is responsible for keeping the COP from
timing out. If the COP times out it is an indication that the software is no longer being executed in the
intended sequence; thus COP reset is generated.
The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL0 and COPOSCSEL1 bit.
In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL0=1 and COPOSCEL1=0 and PCE=1 the
COP continues to run, else the COP counter halts in Stop Mode with COPOSCSEL1 =0.
In Pseudo Stop Mode and Full Stop Mode with COPOSCSEL1=1 the COP continues to run.
Table 10-28.gives an overview of the COP condition (run, static) in Stop Mode depending on legal
configuration and status bit settings:
)
(
)
PLLCLK
512 cycles
256 cycles
S12_CPMU drives
possibly
RESET
driven
low
)
(
(
RESET
S12_CPMU releases
f
VCORST
RESET pin low
RESET
pin
f
VCORST