48 KByte Flash Module (S12FTMRG48K1V1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 879
26.3.2.5 Flash Configuration Register (FCNFG)
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU.
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
26.3.2.6 Flash Error Configuration Register (FERCNFG)
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
Offset Module Base + 0x0004
76543210
R
CCIE
00
IGNSF
00
FDFD FSFD
W
Reset00000000
= Unimplemented or Reserved
Figure 26-9. Flash Configuration Register (FCNFG)
Table 26-13. FCNFG Field Descriptions
Field Description
7
CCIE
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see Section 26.3.2.7)
4
IGNSF
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section 26.3.2.8).
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
generated
1
FDFD
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD.
0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Section 26.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG
register is set (see Section 26.3.2.6)
0
FSFD
Force Single Bit Fault Detect
— The FSFD bit allows the user to simulate a single bit fault during Flash array
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see Section 26.3.2.7)
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section 26.3.2.6)
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