NXP Semiconductors MC9S12G - Page 386

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
388 NXP Semiconductors
CPMUSYNR, CPMUREFDIV, CPMUCLKS, CPMUPLL, CPMUIRCTRIMH/L and CPMUOSC
Read: Anytime
Write: Anytime
10.3.2.21 Reserved Register CPMUTEST2
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in Special
Mode can alter the S12CPMU’s functionality.
Read: Anytime
Write: Only in Special Mode
0x02FB
76543210
R0000000
PROT
W
Reset00000000
Figure 10-28. S12CPMU Protection Register (CPMUPROT)
Field Description
0
PROT
Clock Configuration Registers Protection Bit — This bit protects the clock configuration registers from
accidental overwrite (see list of affected registers above):
Writing 0x26 to the CPMUPROT register clears the PROT bit, other write accesses set the PROT bit.
0 Protection of clock configuration registers is disabled.
1 Protection of clock configuration registers is enabled. (see list of protected registers above).
0x02FC
76543210
R0 0 0 0 0 0 0 0
W
Reset00000000
= Unimplemented or Reserved
Figure 10-29. Reserved Register CPMUTEST2