S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
380 NXP Semiconductors
10.3.2.15 Autonomous Clock Trimming Register (CPMUACLKTR)
The CPMUACLKTR register configures the trimming of the Autonomous Clock (ACLK - trimmable
internal RC-Oscillator) which can be selected as clock source for some CPMU features.
Read: Anytime
Write: Anytime
10.3.2.16 Autonomous Periodical Interrupt Rate High and Low Register
(CPMUAPIRH / CPMUAPIRL)
The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical
interrupt rate.
0x02F3
76543210
R
ACLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0
00
W
ResetFFFFFF00
After de-assert of System Reset a value is automatically loaded from the Flash memory.
Figure 10-19. Autonomous Periodical Interrupt Trimming Register (CPMUACLKTR)
Table 10-17. CPMUACLKTR Field Descriptions
Field Description
7–2
ACLKTR[5:0]
Autonomous Clock Trimming Bits — See Table 10-18 for trimming effects. The ACLKTR[5:0] value
represents a signed number influencing the ACLK period time.
Table 10-18. Trimming Effect of ACLKTR
Bit Trimming Effect
ACLKTR[5] Increases period
ACLKTR[4] Decreases period less than ACLKTR[5] increased it
ACLKTR[3] Decreases period less than ACLKTR[4]
ACLKTR[2] Decreases period less than ACLKTR[3]
ACLKTR[1] Decreases period less than ACLKTR[2]
ACLKTR[0] Decreases period less than ACLKTR[1]
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