NXP Semiconductors MC9S12G - Page 379

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 381
Read: Anytime
Write: Anytime if APIFE=0. Else writes have no effect.
The period can be calculated as follows depending on logical value of the APICLK bit:
APICLK=0: Period = 2*(APIR[15:0] + 1) * ACLK Clock Period
APICLK=1: Period = 2*(APIR[15:0] + 1) * Bus Clock period
NOTE
For APICLK bit clear the first time-out period of the API will show a
latency time between two to three f
ACLK
cycles due to synchronous clock
gate release when the API feature gets enabled (APIFE bit set).
0x02F4
76543210
R
APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8
W
Reset00000000
= Unimplemented or Reserved
Figure 10-20. Autonomous Periodical Interrupt Rate High Register (CPMUAPIRH)
0x02F5
76543210
R
APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0
W
Reset00000000
Figure 10-21. Autonomous Periodical Interrupt Rate Low Register (CPMUAPIRL)
Table 10-19. CPMUAPIRH / CPMUAPIRL Field Descriptions
Field Description
15-0
APIR[15:0]
Autonomous Periodical Interrupt Rate Bits — These bits define the time-out period of the API. See
Table 10-20 for details of the effect of the autonomous periodical interrupt rate bits.
Table 10-20. Selectable Autonomous Periodical Interrupt Periods
APICLK APIR[15:0] Selected Period
0 0000 0.2 ms
1
0 0001 0.4 ms
1
0 0002 0.6 ms
1
0 0003 0.8 ms
1