NXP Semiconductors MC9S12G - Page 380

S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
382 NXP Semiconductors
10.3.2.17 Reserved Register CPMUTEST3
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in Special
Mode can alter the S12CPMU’s functionality.
Read: Anytime
Write: Only in Special Mode
0 0004 1.0 ms
1
0 0005 1.2 ms
1
0 ..... .....
0 FFFD 13106.8 ms
1
0 FFFE 13107.0 ms
1
0 FFFF 13107.2 ms
1
1 0000 2 * Bus Clock period
1 0001 4 * Bus Clock period
1 0002 6 * Bus Clock period
1 0003 8 * Bus Clock period
1 0004 10 * Bus Clock period
1 0005 12 * Bus Clock period
1 ..... .....
1 FFFD 131068 * Bus Clock period
1 FFFE 131070 * Bus Clock period
1 FFFF 131072 * Bus Clock period
1
When f
ACLK
is trimmed to 10KHz.
0x02F6
76543210
R00000000
W
Reset00000000
= Unimplemented or Reserved
Figure 10-22. Reserved Register (CPMUTEST3)
Table 10-20. Selectable Autonomous Periodical Interrupt Periods (continued)
APICLK APIR[15:0] Selected Period