NXP Semiconductors MC9S12G - Page 117

Device Overview MC9S12G-Family
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 119
57 PS5 MOSI0 — — — V
DDX
PERS/PPSS Up
58 PS6 SCK0 — — — V
DDX
PERS/PPSS Up
59 PS7 API_EXTC
LK
ECLK SS0
—V
DDX
PERS/PPSS Up
60 PM0 RXCAN — — — V
DDX
PERM/PPSM Disabled
61 PM1 TXCAN — — — V
DDX
PERM/PPSM Disabled
62 PM2 RXD2 — — — V
DDX
PERM/PPSM Disabled
63 PM3 TXD2 — — — V
DDX
PERM/PPSM Disabled
64 PJ7 KWJ7 SS2
——V
DDX
PERJ/PPSJ Up
1
The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled
Table 1-27. 64-Pin LQFP Pinout for S12G192 and S12G240
Function
<----lowest-----PRIORITY-----highest---->
Power
Supply
Internal Pull
Resistor
Package Pin Pin
2nd
Func.
3rd
Func.
4th
Func
5th
Func
CTRL
Reset
State