NXP Semiconductors MC9S12G - Page 1228

Electrical Characteristics
MC9S12G Family Reference Manual Rev.1.27
1230 NXP Semiconductors
In Figure A-10 the timing diagram for slave mode with transmission format CPHA = 1 is depicted.
Figure A-10. SPI Slave Timing (CPHA = 1)
SCK
(Input)
SCK
(Input)
MOSI
(Input)
MISO
(Output)
1
5 6
MSB IN
Bit MSB-1 . . . 1
LSB IN
MSB OUT Slave LSB OUT
Bit MSB-1 . . . 1
4
4
9
12 13
11
(CPOL = 0)
(CPOL = 1)
SS
(Input)
2
12 13
3
NOTE: Not defined
Slave
7
8
See
Note