NXP Semiconductors MC9S12G - Page 124

Device Overview MC9S12G-Family
MC9S12G Family Reference Manual Rev.1.27
126 NXP Semiconductors
2VDDXR——— —— — —
3 VSSX — — — — — — —
4PE0
1
EXTAL — — — V
DDX
PUCR/PDPEE Down
5VSS——— —— — —
6PE1
1
XTAL — — — V
DDX
PUCR/PDPEE Down
7 TEST — — — — N.A. RESET
pin Down
8 PJ0 KWJ0 PWM6 MISO1 — V
DDX
PERJ/PPSJ Up
9 PJ1 KWJ1 IOC6 MOSI1 — V
DDX
PERJ/PPSJ Up
10 PJ2 KWJ2 IOC7 SCK1 — V
DDX
PERJ/PPSJ Up
11 PJ3 KWJ3 PWM7 SS1
—V
DDX
PERJ/PPSJ Up
12 BKGD MODC — — — V
DDX
PUCR/BKPUE Up
13 PP0 KWP0 ETRIG0 API_EXTC
LK
PWM0 V
DDX
PERP/PPSP Disabled
14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V
DDX
PERP/PPSP Disabled
15 PP2 KWP2 ETRIG2 PWM2 — V
DDX
PERP/PPSP Disabled
16 PP3 KWP3 ETRIG3 PWM3 — V
DDX
PERP/PPSP Disabled
17 PP4 KWP4 PWM4 — — V
DDX
PERP/PPSP Disabled
18 PP5 KWP5 PWM5 — — V
DDX
PERP/PPSP Disabled
19 PT5 IOC5 — — — V
DDX
PERT/PPST Disabled
20 PT4 IOC4 — — — V
DDX
PERT/PPST Disabled
21 PT3 IOC3 — — — V
DDX
PERT/PPST Disabled
22 PT2 IOC2 — — — V
DDX
PERT/PPST Disabled
23 PT1 IOC1 IRQ
——V
DDX
PERT/PPST Disabled
24 PT0 IOC0 XIRQ
——V
DDX
PERT/PPST Disabled
25 PAD0 KWAD0 AN0 — — V
DDA
PER1AD/PPS1AD Disabled
26 PAD8 KWAD8 AN8 — — V
DDA
PER0AD/PPS0AD Disabled
27 PAD1 KWAD1 AN1 — — V
DDA
PER1AD/PPS1AD Disabled
28 PAD9 KWAD9 AN9 — V
DDA
PER0AD/PPS0AD Disabled
29 PAD2 KWAD2 AN2 — — V
DDA
PER1AD/PPS1AD Disabled
Table 1-29. 48-Pin LQFP Pinout for S12GA192 and S12GA240
Function
<----lowest-----PRIORITY-----highest---->
Power
Supply
Internal Pull
Resistor
Package Pin Pin
2nd
Func.
3rd
Func.
4th
Func
5th
Func
CTRL
Reset
State