Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
166 NXP Semiconductors
PT4 • 48/64/100 LQFP: The TIM channel 4 signal is mapped to this pin when used with the timer function.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output
compare.
• Signal priority:
48/64/100 LQFP: IOC4 > GPO
PT3-PT2 • Except 20 TSSOP: The TIM channels 3 and 2 signal are mapped to these pins when used with the
timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled
output compare.
• Signal priority:
Except 20 TSSOP: IOC3-2 > GPO
PT1 • Except 100 LQFP: The IRQ
signal is mapped to this pin when used with the IRQ interrupt function. If
enabled (IRQCR[IRQEN]=1) the I/O state of the pin is forced to be an input.
• The TIM channel 1 signal is mapped to this pin when used with the timer function. The TIM forces the
I/O state to be an output for a timer port associated with an enabled output compare.
• Signal priority:
100 LQFP: IOC1 > GPO
Others: IRQ
> IOC1 > GPO
PT0 • Except 100 LQFP: The XIRQ signal is mapped to this pin when used with the XIRQ interrupt
function.The interrupt is enabled by clearing the X mask bit in the CPU Condition Code register. The
I/O state of the pin is forced to input level upon the first clearing of the X bit and held in this state even
if the bit is set again. A STOP or WAIT recovery with the X bit set (refer to CPU12/CPU12X Reference
Manual) is not available.
• The TIM channel 0 signal is mapped to this pin when used with the timer function. The TIM forces the
I/O state to be an output for a timer port associated with an enabled output compare.
• Signal priority:
100 LQFP: IOC0 > GPO
Others: XIRQ
> IOC0 > GPO
Table 2-11. Port T Pins PT7-0 (continued)
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