NXP Semiconductors MC9S12G - Page 189

Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 191
2.4.2.3 Block Register Map (G3)
0x027B
PPS1AD
R
PPS1AD7 PPS1AD6 PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0
W
0x027C
PIE0AD
R
PIE0AD7 PIE0AD6 PIE0AD5 PIE0AD4 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0
W
0x027D
PIE1AD
R
PIE1AD7 PIE1AD6 PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0
W
0x027E
PIF0AD
R
PIF0AD7 PIF0AD6 PIF0AD5 PIF0AD4 PIF0AD3 PIF0AD2 PIF0AD1 PIF0AD0
W
0x027F
PIF1AD
R
PIF1AD7 PIF1AD6 PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0
W
Table 2-21. Block Register Map (G3)
Global Address
Register Name
Bit 7654321Bit 0
0x0000–0x0007
Reserved
R00000000
W
0x0008
PORTE
R000000
PE1 PE0
W
0x0009
DDRE
R000000
DDRE1 DDRE0
W
0x000A–0x000B
Non-PIM
Address Range
R
Non-PIM Address Range
W
0x000C
PUCR
R0
BKPUE
0
PDPEE
0000
W
0x000D
Reserved
R00000000
W
= Unimplemented or Reserved
Table 2-20. Block Register Map (G2) (continued)
Global Address
Register Name
Bit 7654321Bit 0
= Unimplemented or Reserved