5V Analog Comparator (ACMPV1)
MC9S12G Family Reference Manual Rev.1.27
252 NXP Semiconductors
3.6.2.2 ACMP Status Register (ACMPS)
5
ACICE
ACMP Input Capture Enable—
Establishes internal link to a timer input capture channel. When enabled, the associated timer pin is disconnected
from the timer input. Refer to ACE description to account for initialization delay on this path.
0 Timer link disabled
1 ACMP output connected to input capture channel 5
4
ACDIEN
ACMP Digital Input Buffer Enable—
Enables the input buffers on ACMPP and ACMPM for the pins to be used with digital functions.
Note: If this bit is set while simultaneously using the pin as an analog port, there is potentially increased power
consumption because the digital input buffer may be in the linear region.
0 Input buffers disabled on ACMPP and ACMPM
1 Input buffers enabled on ACMPP and ACMPM
3-2
ACMOD
[1:0]
ACMP Mode—
Selects the type of compare event setting ACIF.
00 Flag setting disabled
01 Comparator output rising edge
10 Comparator output falling edge
11 Comparator output rising or falling edge
0
ACE
ACMP Enable—
This bit enables the ACMP module and takes it into normal mode (see Section 3.5, “Modes of Operation”). This bit
also connects the related input pins with the module’s low pass input filters. When the module is not enabled, it
remains in low power shutdown mode.
Note: After setting ACE=1 an initialization delay of 63 bus clock cycles must be accounted for. During this time the
comparator output path to all subsequent logic (ACO, ACIF, timer link, excl. ACMPO) is held at its current
state. When resetting ACE to 0 the current state of the comparator will be maintained.
0 ACMP disabled
1 ACMP enabled
Address 0x0261 Access: User read/write
1
1
Read: Anytime
Write:
ACIF: Anytime, write 1 to clear
ACO: Never
76543210
R
ACIF
ACO000000
W
Reset00000000
Figure 3-4. ACMP Status Register (ACMPS)
Table 3-2. ACMPC Register Field Descriptions (continued)
Field Description
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