Background Debug Module (S12SBDMV1)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 285
7.3.2.1 BDM Status Register (BDMSTS)
Figure 7-3. BDM Status Register (BDMSTS)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured, but subject to the following:
— ENBDM should only be set via a BDM hardware command if the BDM firmware commands
are needed. (This does not apply in special single chip mode).
— BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by
the standard BDM firmware lookup table upon exit from BDM active mode.
— All other bits, while writable via BDM hardware or standard BDM firmware write commands,
should only be altered by the BDM hardware or standard firmware lookup table as part of BDM
command execution.
0x3_FF09Reserved R00000000
W
0x3_FF0AReserved R00000000
W
0x3_FF0BReserved R00000000
W
Register Global Address 0x3_FF01
7 6 543 2 1 0
R
ENBDM
BDMACT 0SDVTRACE 0 UNSEC 0
W
Reset
Special Single-Chip Mode 0
1
1
ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but
fully erased (Flash). This is because the ENBDM bit is set by the standard BDM firmware before a BDM command can be fully
transmitted and executed.
1 000 0 0
2
2
UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased,
else it is 0 and can only be read if not secure (see also bit description).
0
All Other Modes 0 0 000 0 0 0
= Unimplemented, Reserved = Implemented (do not alter)
0 = Always read zero
Global
Address
Register
Name
Bit 7654321Bit 0
= Unimplemented, Reserved = Implemented (do not alter)
X
= Indeterminate
0
= Always read zero
Figure 7-2. BDM Register Summary (continued)
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