S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 367
10.3.2.5 S12CPMU Interrupt Enable Register (CPMUINT)
This register enables S12CPMU interrupt requests.
Read: Anytime
Write: Anytime
10.3.2.6 S12CPMU Clock Select Register (CPMUCLKS)
This register controls S12CPMU clock selection.
1
OSCIF
Oscillator Interrupt Flag — OSCIF is set to 1 when UPOSC status bit changes. This flag can only be cleared
by writing a 1. Writing a 0 has no effect.If enabled (OSCIE=1), OSCIF causes an interrupt request.
0 No change in UPOSC bit.
1 UPOSC bit has changed.
0
UPOSC
Oscillator Status Bit — UPOSC reflects the status of the oscillator. Writes have no effect. While UPOSC=0 the
OSCCLK going to the MSCAN module is off. Entering Full Stop Mode UPOSC is cleared.
0 The oscillator is off or oscillation is not qualified by the PLL.
1 The oscillator is qualified by the PLL.
0x0038
76543210
R
RTIE
00
LOCKIE
00
OSCIE
0
W
Reset00000000
= Unimplemented or Reserved
Figure 10-8. S12CPMU Interrupt Enable Register (CPMUINT)
Table 10-4. CPMUINT Field Descriptions
Field Description
7
RTIE
Real Time Interrupt Enable Bit
0 Interrupt requests from RTI are disabled.
1 Interrupt will be requested whenever RTIF is set.
4
LOCKIE
PLL Lock Interrupt Enable Bit
0 PLL LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
1
OSCIE
Oscillator Corrupt Interrupt Enable Bit
0 Oscillator Corrupt interrupt requests are disabled.
1 Interrupt will be requested whenever OSCIF is set.
Table 10-3. CPMUFLG Field Descriptions (continued)
Field Description
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