NXP Semiconductors MC9S12G - Page 52

Device Overview MC9S12G-Family
MC9S12G Family Reference Manual Rev.1.27
54 NXP Semiconductors
16 PAD3 KWAD3 AN3 ACMPO — — — — V
DDA
PER1AD/PPS1AD Disabled
17 PAD4 KWAD4 ETRIG2 PWM2 IOC2 RXD0 AN4 ACMPP V
DDA
PER1AD/PPS1AD Disabled
18 PAD5 KWAD5 ETRIG3 PWM3 IOC3 TXD0 AN5 ACMPM V
DDA
PER1AD/PPS1AD Disabled
19 PS4 ETRIG2 PWM2 RXD0 MISO0 — — — V
DDX
PERS/PPSS Up
20 PS5 IOC2 MOSI0 — — — — — V
DDX
PERS/PPSS Up
1
The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled
Table 1-8. 20-Pin TSSOP Pinout for S12GN16 and S12GN32
Function
<----lowest-----PRIORITY-----highest---->
Power
Supply
Internal Pull
Resistor
Package
Pin
Pin
2nd
Func.
3rd
Func.
4th
Func
5th
Func
6th
Func
7th
Func
8th
Func
CTRL
Reset
State