NXP Semiconductors MC9S12G - Page 588

Scalable Controller Area Network (S12MSCANV3)
MC9S12G Family Reference Manual Rev.1.27
590 NXP Semiconductors
18.3.2.15 MSCAN Receive Error Counter (CANRXERR)
This register reflects the status of the MSCAN receive error counter.
NOTE
Reading this register when in any other mode other than sleep or
initialization mode may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
18.3.2.16 MSCAN Transmit Error Counter (CANTXERR)
This register reflects the status of the MSCAN transmit error counter.
NOTE
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Module Base + 0x000E Access: User read/write
1
1
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)
Write: Unimplemented
76543210
R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
W
Reset:00000000
= Unimplemented
Figure 18-18. MSCAN Receive Error Counter (CANRXERR)
Module Base + 0x000F Access: User read/write
1
1
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)
Write: Unimplemented
76543210
R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
W
Reset:00000000
= Unimplemented
Figure 18-19. MSCAN Transmit Error Counter (CANTXERR)