NXP Semiconductors MC9S12G - Page 647

Pulse-Width Modulator (S12PWM8B8CV2)
MC9S12G Family Reference Manual Rev.1.27
NXP Semiconductors 649
Figure 19-21. PWM 16-Bit Mode
Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the
corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order
bytes PWMEx bits have no effect and their corresponding PWM output is disabled.
PWMCNT6 PWMCNT7
PWM7
Clock Source 7
High Low
Period/Duty Compare
PWMCNT4 PWMCNT5
PWM5
Clock Source 5
High Low
Period/Duty Compare
PWMCNT2 PWMCNT3
PWM3
Clock Source 3
High Low
Period/Duty Compare
PWMCNT0 PWMCNT1
PWM1
Clock Source 1
High Low
Period/Duty Compare
Maximum possible 16-bit channels