NXP Semiconductors MC9S12G - Page 772

16 KByte Flash Module (S12FTMRG16K1V1)
MC9S12G Family Reference Manual Rev.1.27
774 NXP Semiconductors
24.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0).
0x0011
FRSV5
R00000000
W
0x0012
FRSV6
R00000000
W
0x0013
FRSV7
R00000000
W
= Unimplemented or Reserved
Offset Module Base + 0x0000
76543210
RFDIVLD
FDIVLCK FDIV[5:0]
W
Reset00000000
= Unimplemented or Reserved
Figure 24-5. Flash Clock Divider Register (FCLKDIV)
Table 24-7. FCLKDIV Field Descriptions
Field Description
7
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
Address
& Name
76543210
Figure 24-4. FTMRG16K1 Register Summary (continued)