NXP Semiconductors MC9S12G - Page 98

Device Overview MC9S12G-Family
MC9S12G Family Reference Manual Rev.1.27
100 NXP Semiconductors
86 PS4 MISO0 — — V
DDX
PERS/PPSS Up
87 PS5 MOSI0 — — V
DDX
PERS/PPSS Up
88 PS6 SCK0 — — V
DDX
PERS/PPSS Up
89 PS7 API_EXTC
LK
SS0
—V
DDX
PERS/PPSS Up
90 VSSX2 — — — — — —
91 VDDX2 — — — — — —
92 PM0 RXCAN — — V
DDX
PERM/PPSM Disabled
93 PM1 TXCAN — — V
DDX
PERM/PPSM Disabled
94PD4———V
DDX
PUCR/PUPDE Disabled
95PD5———V
DDX
PUCR/PUPDE Disabled
96PD6———V
DDX
PUCR/PUPDE Disabled
97PD7———V
DDX
PUCR/PUPDE Disabled
98 PM2 RXD2 — — V
DDX
PERM/PPSM Disabled
99 PM3 TXD2 — — V
DDX
PERM/PPSM Disabled
100 PJ7 KWJ7 SS2
—V
DDX
PERJ/PPSJ Up
1
The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled
Table 1-22. 100-Pin LQFP Pinout for S12G96 and S12G128
Function
<----lowest-----PRIORITY-----highest---->
Power
Supply
Internal Pull
Resistor
Package Pin Pin
2nd
Func.
3rd
Func.
4th
Func.
CTRL
Reset
State