RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 192 of 765
Mar 7, 2023
Caution 1. Be sure to clear bits 15 to 12, 10, and 8 to 0.
Caution 2. When switching from a function that does not use TImn pin input to one that does, the following
wait period is required from when timer mode register mn (TMRmn) is set until the TSmn (TSHm1,
TSHm3) bit is set to 1.
When the TImn pin noise filter is enabled (TNFENnm = 1):
Four cycles of the operation clock (f
MCK
)
When the TImn pin noise filter is disabled (TNFENnm = 0):
Two cycles of the operation clock (f
MCK
)
Remark 1. When the TSm register is read, 0 is always read.
Remark 2. m: Unit number (m = 0), n: Channel number (n = 0 to 7)
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