RL78/G15 CHAPTER 6 TIMER ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 280 of 765
Mar 7, 2023
Figure 6-74. Block Diagram of Operation as Multiple PWM Output Function (Output Two Types of PWMs)
Interrupt signal
(INTTMmn)
Timer data register mn
(TDRmn)
Timer counter register mn
(TCRmn)
Interrupt
controller
Master channel
(interval timer mode)
TSmn
Slave channel 1
(one-count mode)
TOmp pin
Interrupt signal
(INTTMmp)
Timer data register mp
(TDRmp)
Output
controller
Timer counter register mp
(TCRmp)
Interrupt
controller
CKm0
CKm1
Operation clock
CKm0
CKm1
Operation clock
Slave channel 2
(one-count mode)
TOmq pin
Interrupt signal
(INTTMmq)
Timer data register mq
(TDRmq)
Output
controller
Timer counter register mq
(TCRmq)
Output
controller
CKm0
CKm1
Operation clock
Clock selection
Trigger
selection
Clock selection
Trigger
selection
Clock selection
Trigger
selection
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4)
p: Slave channel number, q: Slave channel number
n < p < q ≤ 7 (Where p and q are integers greater than n)