Renesas RL78/G15

RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 367 of 765
Mar 7, 2023
Figure 12-1 shows the block diagram of serial array unit 0.
Figure 12-1. Block Diagram of Serial Array Unit 0
Serial clock
I/O pin
Serial data I/O pin
(when CSI01: SI01)
(when IIC01: SDA01)
f
CLK
/2
0
- f
CLK
/2
15
0
(Clock division setting block)
Serial data register 00 (SDR00)
Serial mode register 00 (SMR00)
Serial communication operation setting register 00 (SCR00) Serial status register 00 (SSR00)
Error
information
Clear
Serial flag clear trigger
register 00 (SIR00)
f
TCLK
f
MCK
f
SCK
f
CLK
/2
0
- f
CLK
/2
15
f
CLK
Serial clock I/O pin
(when CSI01: SCK01)
(when IIC01: SCL01)
When UART0
Serial data
input pin
(when CSI00:
SCK00)
(when IIC00:
SCL00)
Serial transfer error interrupt
(INTSRE0)
Serial transfer end interrupt
(when CSI01: INTCSI01)
(when IIC01: INTIIC01)
(when UART0: INTSR0)
Serial data output pin
(when CSI01: SO01)
(when IIC01: SDA01)
Serial transfer end interrupt
(when CSI00: INTCSI00)
(when IIC00: INTIIC00)
(when UART0: INTST0)
Serial data output pin
(when CSI00: SO00)
(when IIC00: SDA00)
(when UART0: TxD0)
Output latch
(P11 or P12)
Noise filter enable
register 0 (NFEN0)
Serial output level
register 0 (SOL0)
Serial output enable
register 0 (SOE0)
Serial channel stop
register 0 (ST0)
Serial channel start
register 0 (SS0)
Serial channel
enable status
register 0 (SE0)
PRS
013
Peripheral enable
register 0
(PER0)
Serial clock select register 0 (SPS0)
Serial output register 0 (SO0)
TXE
00
4
4
PM10
CK01 CK00
Output latch
(P10)
CK01 CK00
SNFEN00
Edge/level
detection
Selector
Error
controller
Prescaler
Communication
controller
Mode selection
CSI01 or IIC01 or
UART0
(for reception)
Error controller
Communication controller
Mode selection
CSI00 or IIC00 or
UART0 (for
transmission)
Output
controller
Interrupt
controller
Shift register
Edge/
level
detection
0
0
0
0
0
CKO01
CKO00
0
0
0
0
0
0
SO01 SO00
SE01 SE00
SS01 SS00
ST01
ST00
SOE01
SOE00
0
SOL00
SNFEN
00
SAU0EN
SelectorSelector
PRS
012
PRS
011
PRS
010
PRS
003
PRS
002
PRS
001
PRS
000
Channel 0
Synchro-
nous
circuit
Edge
detection
(Buffer register block)
Noise
elimination
enabled/
disabled
Synchro-
nous
circuit
Channel 1
Synchro-
nous
circuit
RXE
00
DAP
00
CKP
00
EOC
00
PTC
001
PTC
000
DIR
00
SLC
001
SLC
000
DLS
001
DLS
000
CKS00
CCS00
STS00
SIS00
MD002
MD001
MD000
TSF
00
BFF
00
PEF
00
OVF
00
PECT
00
OVCT
00
State of communications
PM11 or PM12
(when CSI00: SI00)
(when IIC00: SDA00)
(when UART0: RxD0)
Selector
Selector
Clock controller