RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 411 of 765
Mar 7, 2023
(2) Operation procedure
Figure 12-30. Initial Setting Procedure for Master Reception
Release the serial array unit from the reset state
,
and
start clock supply to the serial array unit
.
Starting initial setting
Setting the PER
0
register
Setting the SPSm register
Setting the SMRmn register
Setting the SCRmn register
Setting the SDRmn register
Setting the SOm register
Setting port
Writing to the SSm register
Completing initial setting
Set the operation clock
.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the transfer clock by
dividing the operation clock (f
MCK
)).
Set the initial output level of the serial clock
(CKOmn).
Enable clock output of the target channel by setting
a port register and a port mode register.
Set the SSmn bit of the target channel to 1
(SEmn bit
= 1:
to enable operation).
Initial setting is completed
.
Set dummy data to the SIOp register (bits
7 to 0
of
the SDRmn register) and start communication
.
Figure 12-31. Procedure for Stopping Master Reception
Starting setting to stop
Writing the STm register
Changing setting of the SOEm
register
Changing setting of the SOm
register
Setting the PER0 register
Stop setting is completed
If there is any data being transferred, wait for their completion.
(If there is an urgent must stop, do not wait.)
Write 1 to the STmn bit of the target channel
(stopping operation by setting SEmn = 0).
Set the SOEmn bit to 0 and stop the output of
the target channel.
The levels of the serial clock (CKOmn) on the target
channel can be changed if necessitated by an
emergency.
Stop clock supply to the serial array unit, and reset
the serial array unit.
After the stop setting is completed, go to the next
processing.
(Essential)
TSFmn = 0?
No
Yes
(Selective)
(Essential)
(Selective)
(Selective)
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