RL78/G15 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0959EJ0110 Rev.1.10 Page 473 of 765
Mar 7, 2023
(2) Operation procedure
Figure 12-77. Initial Setting Procedure for UART Reception
Release the serial array unit from the reset state, and
start clock supply to the serial array unit.
Starting initial setting
Setting the PER0 register
Setting the SPSm register
Setting the SMRmn and SMRmr
registers
Setting the SCRmn register
Setting the SDRmn register
Setting port
Writing to the SSm register
Completing initial setting
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the transfer clock by
dividing the operation clock (f
MCK
)).
Enable data input of the target channel by setting a port
register and a port mode register.
Set the SSmn bit of the target channel to 1 and
set the SEmn bit to 1 (to enable operation).
Become wait for start bit detection.
Caution Set the RXEmn bit of SCRmn register to 1, and then be sure to set SSmn to 1 after at least 4 f
MCK
clock
cycles have elapsed.
Figure 12-78. Procedure for Stopping UART Reception
Starting setting to stop
Writing the STm register
Setting the PER0 register
Stop setting is completed
If there is any data being transferred, wait for their
completion. (If there is an urgent must stop , do not wait).
Write 1 to the STmn bit of the target channel
(stopping operation by setting SEmn = 0).
Stop clock supply to the serial array unit, and
reset the serial array unit.
After the stop setting is completed, go to the next
processing.
TSFmn = 0?
No
Yes
(Selective)
(Essential)
(Selective)
To Next Page
Loading...
Need help?
General
